1. Field of the Invention
The present invention relates to semiconductor packages and fabrication methods thereof, and more particularly, to a semiconductor package having passive elements and a fabrication method thereof.
2. Description of Related Art
The development of electronic products having small size and high performance requires IC elements having high memory capacities, high frequencies and low voltages. Further, the development of IC elements having high memory capacities, high frequencies and low voltages depends on the integration degree of electronic circuits and electronic elements of the IC elements and the density of I/O connectors used for signal transmission.
Currently, BGA type semiconductor devices capable of accommodating a large number of passive elements, such as capacitors, resistors, inductors and oscillators, have become a mainstream.
In some semiconductor application devices, such as communication or high-frequency semiconductor devices, semiconductor chips need to be electrically connected to passive elements, such as resistors, inductors, capacitors and oscillators, so as to obtain certain electric current characteristics or send certain signals.
FIG. 1 is a schematic perspective view of a conventional BGA type semiconductor device. Referring to FIG. 1, a plurality of passive elements 11 and a plurality of semiconductor chips 12 are disposed on a surface of a substrate 10. To facilitate electrical connection between the semiconductor chips 12 and bonding fingers (not shown) of the substrate 10, the passive elements 11 are generally positioned at corners of the substrate 10 or outside chip mounting areas of the substrate 10. However, the limited positions of the passive elements 11 reduce the wiring flexibility of the substrate 10 and the limited positions of the boning fingers restrict the number of the passive elements 11 that can be disposed on the substrate 10, thereby hindering the development of highly integrated semiconductor devices. On the other hand, if the surface area of the substrate 10 is increased to accommodate a large number of passive elements 11 and semiconductor chips 12, the size of the final package will be increased. As such, it cannot meet the trend of miniaturization.
Accordingly, another conventional BGA type semiconductor device is provided. Referring to FIG. 2, a plurality of passive elements 22 are disposed between a semiconductor chip 23 and bonding fingers of the substrate. However, as the number of I/O connectors in a unit area of the semiconductor device increases, the number of bonding wires 21 also increases. Generally, the height of the passive elements 22 (e.g. 0.8 mm) is higher than the height of the semiconductor chip 23 (e.g., 0.55 mm). Therefore, to prevent the bonding wires 21 from coming into contact with the passive elements 22, the bonding wires must be positioned high above the passive elements 22, thus increasing the bonding difficulty and processing complexity. Also, wire loops of the bonding wires 21 are increased and consequently the fabrication cost of the bonding wires 21 is increased. Further, the bonding wires 21 at high positions easily sag due to lack of support. As such, the bonding wires 21 easily come into contact with the passive elements 22 and cause a short circuit to occur.
Therefore, how to overcome the above-described drawbacks has become critical.